1. Field of the Invention
The present invention relates to high density semiconductor memory devices and more particularly, to a circuit for applying a pumped voltage which is greater than the source supply voltage, to components within the high density semiconductor memory devices.
2. Description of the Related Art
The complexity of semiconductor memory devices has rapidly increased so that memory devices having a capacity of several tens of mega bits (Mbit) are fabricated under design tolerances of 1-micron (micrometer) or less.
Such semiconductor memory devices comprise mostly a plurality of CMOS elements having operating voltages applied across thin dielectric films.
As the complexity increases, the space between CMOS elements or signal lines is reduced along with the thickness of the dielectric films. Thus, it becomes necessary to lower chip operating voltage.
For example, 64 Mbit memory devices usually have an operating voltage of 1.5V. However, if the operating voltage of the memory device is improvidently lowered, the voltage drop caused by the threshold voltage of the respective MOS transistors and the resistances of signal lines during the transmission of data signals will often make it impossible to read and write the data.
In order to solve this problem, the externally applied source voltage is amplified within the chip of the memory device. Such amplifying means are better known as pumping circuits, bootstrapping circuits or voltage-raising circuits. For consistency, in the present application, such a circuit will be referred to as a pumping circuit.
As shown in FIG. 1A which illustrates a conventional pumping circuit, enable clock pulses are applied to drive circuit 1, 2 and to a first electrode of a pumping capacitor 3, providing at the other electrode a pumped voltage Vpp which is increased by coupling to a voltage level greater than that of the voltage applied to the first electrode.
Although this pumping circuit has a simple structure, there is not provided a way for stabilizing the output of pumping capacitor 3. Therefore, its operational reliability decreases when used in high density memory devices which demand a much lower operating voltage. Moreover, it is also difficult to adjust the timing of the enable clock pulses.
In order to improve the pumping circuit of FIG. 1A, a voltage pumping circuit as shown in FIG. 1A, originally disclosed in the IEEE JOURNAL OF SOLID-STATE CIRCUIT, VOL.24, NO.3, JUNE 1989, has been proposed.
In FIG. 1B, .PHI.PHB represents a word line precharge signal, .PHI.1 and .PHI.2 represent clock signals to enable row address signals, and OSC represents an oscillator output. When the chip is enabled from standby, i.e., precharging is performed before and after a read/write operation, the word line precharge signal .PHI.PHB is set to level Vpp. In the operational mode of the chip, the signal .PHI.PHB is supplied with ground voltage level (0V).
As shown in FIG. 1B, if the voltage level of word line precharge signal .PHI.PHB drops from Vpp level to OV, clock signals .PHI.1 and .PHI.2 are raised to Vcc level. Subsequently, clock signal .PHI.1 initiates a coupling effect on capacitors C1 and C2 to pump the voltages of signal lines G1 and G2 to level Vcc level or even greater. Similarly, clock signal .PHI.2 initiates a coupling effect on capacitors C3 and C4 to pump the voltages of signal lines G3 and G4 to a level Vpp which is greater than level Vcc.
Thereafter, the pumped voltages of signal lines G1 and G2 are dropped to 0V by clock signal .PHI.2. The voltages of signal lines G3 and G4 represent the output Vpp. As the chip changes its state from operational mode to standby mode, word line precharge signal .PHI.PHB is applied with voltage Vpp level. As a result, the output of prior art FIG. 1B results in voltage level Vcc, the voltage Vpp level being produced only when a given row address signal is applied active (operational mode).
Although the circuit of FIG. 1B overcomes tile problems associated with unstable Vpp voltages and the imprecise timing of input signal response, other problems originate. Namely, additional circuits necessary for generating the word line precharge signal .PHI.PHB and clock signals .PHI.1 and .PHI.2 are required. The addition of further non-memory circuitry reduces memory capacity and degrades chip density.
Moreover, voltage Vpp is output when a row address signal is applied active, enabling clock signals .PHI.1 and .PHI.2 and thereby degrading the operational speed of the chip.
Additionally, the circuit of FIG. 1B provides poor voltage pumping efficiency when used with semiconductor memory devices of densities in the order of 16 Mbits or 64 Mbits.
FIG. 1C shows another conventional voltage pumping circuit proposed by Yoshinobu Nakakome, et al in an article entitled "An Experimental 1.5-V 64 Mbit DRAM", IEEE Journal of Solid State Circuits, Vol.26, No.4, April 1991, pp.465-472. This article discloses a word line driver circuit for preventing the word line voltage from being dropped by a threshold voltage of an access transistor.
As shown in FIG. 1C, the word line driver produces a pumped voltage V.sub.CH of voltage level 2Vcc by a feedback operation of charge pump circuits CP1 and CP2 even under low operating voltage conditions. This circuit, however, exhibits the following problems:
First, the capacitance of capacitor CcH connected to node VcH becomes so great that the area of the chip is increased. When a voltage "high" level is transferred to a selected word line, charge sharing occurs between capacitor C.sub.CH and the capacitance component C.sub.WL of the word line. This relationship may be expressed by the following equation (1): EQU C.sub.CH .times.V.sub.CH =(C.sub.WL +C.sub.CH).times.V.sub.WL EQU V.sub.WL =[C.sub.CH /(C.sub.WL +C.sub.CH)].times.V.sub.CH ( 1)
From equation (1), we can see that it is preferable for voltage V.sub.WL of the word line to equal the pumped voltage V.sub.CH. Capacitance C.sub.CH should be of a great enough value to obviate capacitance C.sub.WL. After charge sharing, the voltage drop of node V.sub.CH should be small to secure the stable operation of the circuit in the next cycle. This is achieved by making capacitance CcH great.
Second, in order to set the voltage of a selected word "high", the voltage pumping circuit is kept operating to charge node V.sub.CH, increasing chip power consumption.
Moreover, the continuous operation of the voltage pumping circuit of FIG. 1C may excessively increase the voltage at node V.sub.CH and destroy adjacent transistors.